execute this program, the user must have prepared two input files: one that
holds the various configuration parameters, and one that holds the truthtable
that the program will strive to emulate with each successive generation.
Details for properly writing either file is covered in the User's Manual.
files are in place, the program can be executed. It begins by creating a seed
generation that is wholly random. It obeys the user's criteria for number of
inputs, outputs, circuit components, and so forth. This generation is comprised
by many iterations, each of which represents a single circuit in graph form.
This graph is written out as a .dot file, and then converted into a VHDL file.
A VHDL testbench runs this file using input gathered from the supplied
truthtable and generates output. The output is tested against the expected
output and a grade is then assigned. Graded circuits are sorted in descending
order, and a user-supplied amount will be selected for merging. The program
then enters into the next generation.
The user may
select how many generations he wishes to run. So long as more than one is
selected, there will be merging of the previous generation's best scoring
circuits into new, derived circuits. These circuits are again represented by
graphs, which are converted to VHDL files and follow the same path of execution
as the seed generation. The program will continue to run so long as it has more
generations to process.
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